1. Field of Invention
The present invention relates to a method for determining an overlay correlation set. More particularly, the present invention relates to a method for determining an overlay correlation set with excluding manufacturing variables.
2. Description of Related Art
In the manufacture of integrated circuit, photolithography process is used to transfer patterns from a photo mask having customized circuit patterns to thin films formed on a wafer. The image transfer process comprises steps of forming a photoresist layer on a non-process layer, illuminating the photoresist layer through a photo mask having the customized circuit patterns, developing the photoresist layer and then etching the non-process layer by using the patterned photoresist layer as a mask. Hence, the image transfer process is accomplished. For a well-manufactured integrated circuit product, the image transfer process mentioned above is performed several times to transfer the circuit patterns to each non-process layers to form the electrically circuit device. Therefore, it is important to align the successive patterned layers to reduce the misalignment errors as the critical dimension of the semiconductor device becomes smaller and smaller.
Typically, the overlay correlation set in an exposure tool is used to insure the alignment precision between the successive patterned layers. However, the overlay correlation set is seriously affected by the manufacturing variables. FIG. 1 is a cross-sectional view of the overly mark and the distortion phenomenon due to the self-shadowing effect. FIG. 2 is a top view showing the overlay results between two patterned successive material layers in different positions on a wafer. During a material film is formed by performed a deposition process, the incident angles of deposited particles on both sidewalls of the overlay mark is different. The incident angles of the deposited particles become large from the wafer center to the wafer edge. Accordingly, the thicknesses of the material film on both sidewalls of the overlay mark are different and the unbalanced thicknesses at both sidewalls of the overlay mark become serious from the wafer center to the wafer edge. Hence, the phenomenon of the unbalanced thickness on both sidewalls of the overlay mark is known as the self-shadowing effect. As shown in FIG. 1, during the formation of a material layer 106 over a material layer 102 having an overlay mark 104 on a substrate, the self-shadowing effect happens and becomes more obvious from the wafer center to the wafer edge. Because the position which the material target for forming the material layer 106 is located is over the wafer, the atom accumulations at both sidewalls of the overlay mark are getting asymmetric from the wafer center to the wafer edge. Therefore, the center line A of the overlay mark 104 shifts to line B with a shifting amount Δx after the material layer 106 is formed. The shifting amount Δx is a function of wafer location. Usually, Δx is zero at the wafer center and is increased from the wafer center to the wafer edge. This kind of overlay offset phenomenon is known as pattern scaling effect. Because the line A of the overlay mark 104 shifts to line B with a shifting amount Δx, the photomask for patterning the material 106 misaligns with the overlay mark 104 for with a shifting amount Δx. Therefore, the successive patterned material layers misaligns with each other with a shifting amount Δx.
As shown in FIG. 2, at the center region 202 of the wafer 200, the overlay between the element 210a and the element (not shown) under the element 210a is well controlled since the material target (not shown) is right above the center region 202 of the wafer 200. However, because the self-shadowing effect is more serious at the wafer edge 204, the element 210b partially covers the element 208b. Similarly, at the wafer edge 206, the element 210c partially covers the element 208c. Apparently, the partial covering between the element 210b and 208b at left-hand side of the wafer 200 is a mirror image of the partial covering between the element 210c and 208c at right-hand side of the wafer 200. Hence, for a single wafer, the alignment quality over the entire wafer is not consistent. Although the real shifting amount can be inspected in the after etching inspection (AEI), it is too late to rework the patterned material layer with a poor overlay performance after the etching process.
FIG. 3A is a Target Life-Time plot diagram. FIG. 3B is a Shifting amount-Time plot diagram. As shown in FIG. 3A and FIG. 3B, the shifting amount due to the self-shadowing effect is seriously affected by the life time of the material target for forming the material layer 106. That is, in the same region of the wafer, the shifting amount is not steady and varies with the target life time. Hence, even the overlay correlation set can be feedback compensated through AEI to adjust the alignment precision, the shifting amount changing from time to time makes the alignment process become more difficult to be controlled and predicted.